OLEDs have recently shown promise for use as a light source in optical displays. A typical structure for an OLED is shown in FIG. 1 and consists of a stack of organic semiconductor layers 10 between a transparent electrode 12 (usually an indium tin oxide (ITO) layer acting as an anode) on a glass substrate 14 and another electrode 16 (usually a layer of low work function metal, metal alloy or cermet material acting as a cathode). At positive bias, electric current will flow through the device and light emission will occur between the overlapped area of anode and cathode.
In order to display information, it is necessary to make pixels of the required shape. This can be achieved either by patterning the first electrode (anode) or using shadow masks to define the shape of the second electrode, or patterning both electrodes depending on the application.
The vertical dimension of organic light emitting devices (OLED) is usually very thin. To optimize the hole-transport, electron-transport properties and device efficiency, the total thickness of the organic layer between the cathode and anode is typically between 100 nm and 200 nm. A typical OLED has an electric field of ˜106V/cm during device operation. This high electric field makes OLEDs very sensitive to the edges of patterned ITO substrates (the first electrode) or other types of electrode on which the organic materials is deposited. Imperfect step coverage of the deposited organic materials will result in a substantially higher electric field and higher local current density at that area. This will cause the device to break down.
FIG. 2 shows an anode 12 that has been patterned for form three OLED devices 20a, 20b, 20c. The lack of anode material between the devices causes a step between the portions of the deposited cathode layer 16a and organic layer 10a located between the OLED devices and between the portions of the same layers, 16b, 10b over the OLED devices. FIG. 2 shows that in some cases the patterned ITO layer 12 or other type of electrode layer is thicker than the organic layer 10. Since thermal vacuum deposition, which is used to deposit the organic layer 12, is generally non-conformal, some uncovered ITO anode area 21 will come into contact with the metal cathode layer 16 deposited after the deposition of the organic layers 12. This will cause massive short circuits in the devices.
Because of the non-conformal nature of the thermal deposition, when the total thickness of ITO anode and organic layers exceeds the thickness of the cathode layer, a discontinuity 22 may occur in cathode layer where it passes from the OLED to the area between the OLEDs. This type of discontinuity will cause device failure in OLEDs based on a common cathode (or common anode) design and may also cause device failure in individual pixels or segments due to the open circuit between the electrode layer and connection pads.
Deposited silicon oxide, aluminum oxide, or silicon nitride is typically used to define an emissive area. After the deposition of insulating material, a photolithographic process and an etching process are necessary to create pixel areas and sloped edges. Such a process is described in U.S. Pat. No. 6,069,443, the contents of which are herein incorporated by reference. This process is complicated. It involves dielectric deposition, a photolithographic process, and at least one etching step for creating pixel areas. The deposition of dielectric material is also expensive.
Various solutions have been proposed in the prior art, all of which are unsatisfactory for one reason or another. Mathine et al (U of Arizona) [D. L. Mathine et al, Appl. Phys. Lett., 76(26), 2000, p 3849], describes the use of PEDOT:PSS (poly(ethylened ioxythiophene) doped with polystyrenesulfonate) as a buffer layer between a CMOS active matrix and the OLED. It is spun-5 on and forms a 20 nm thick conformal layer that covers the dielectric edges between pixels. It is resistive enough not to short the different pixels, and helps charge injection into the hole transport layer. A lift-off photoresist pattern is applied prior to PEDOT/PSS so that layer can be lifted off the connection pads. The layer is too thin to smooth out underlying structures and is actually part of the diode.
Shimoda (Seiko, CDT) [Asia Display 98, p 2171 use an SiO2 “adhesive” layer and a polyimide “interval layer” between a TFT active matrix and the PLEDs. Both have openings that define the pixels. Shimoda's layer is an insulating and passivation layer. The edges are not sloped.
Steward et al (U of Lehigh and Emagin, old FED Corp) [IEDM 98, p 871] use two spin-on-glass layers for planarization of a TFT matrix. The first layer goes below the ITO anode to ensure planarity of the ITO electrode on top of the matrix, and the second layer defines pixel openings and smoothes the matrix. The SOG layers are spun, cured at 300° C., patterned and wet-etched in a certain way so that the organic materials have good step coverage.
Jones (Emagin, old FED Corp) [U.S. Pat. No 6,069,443] describes the use of a separator for passive matrix displays with an overhanging profile and an underlying insulator that prevents short-circuits from happening when the cathode flows on top of the organics edge defined by the overhanging separator. Jones employs an underlying insulator with openings that substantially define pixels, and with tapered edges to minimize edge shorts. The purpose of Jones' structure is to prevent short-circuits.
Smoothing layers have been used in LCDs between the color filters, patterned first on the substrate, and the ITO electrode (see for example U.S. Pat. No. 5,488,497). In this case the goal is to ensure color purity and has nothing to do with field homogeneity since liquid crystal layers are very thick compared to the thickness of the electrodes.